a. Assuming that the mobility of electrons in the channel is about three times that of holes, what..
a. Assuming that the disturbance of electrons in the muniment is environing three times that of holes, what must the width of the pMOS transistor (Wp) be for the two transistors to evidence the corresponding trans conductance factors (that is, n = p)?
b. Intuitively, externally inspecting Equation 9.7, would you wait-for the transition voltage to veer inside 0 V or VDD when (W/L)n is increased delay regard to (W/L)p? Explain.
c. If n > p, stately that VTn = VTp, do you wait-for the transition voltage to be higher or inferior than VDD/2?