a. The circuit of Figure E4.25 shows a wired gate constructed with open-drain buffers (note that the
a. The circuit of Figure E4.25 shows a wired portico fabricated delay open-drain buffers (still n ess that the interior buffers are inverters). What kind of portico is this?
b. When y is low (~0 V), prevalent flows through the 10 k pull-up resistor. What is the power dissipated by this resistor when merely one nMOS transistor is ON? And when all are ON?