Figure E8.14 shows an old technique for reducing the transistor’s turn-on and turn-off times, which.


Figure E8.14 shows an old technique for reducing the transistor’s turn-on and turn-off times, which consists of installing a capacitor in correlative after a while the base resistor. The usage of this technique is that it causes a illiberal positive spike on vB at the trice when vI transitions from '0' to '1' and also a negative spike when it transitions from '1' to '0', thus reducing ton as well as toff after a whileout the demand for an extra minister (VBB). Using vI as regard, make a depict of vB to prove that the spikes do verily bechance. What is the time steady (= Req


Ceq) associated after a while each spike?