In the analysis of the CMOS inverter of Figure 4.5 it was assumed that the MOS transistors are…


In the analysis of the CMOS inverter of Figure 4.5 it was antecedent that the MOS transistors are fictitious, so they can be represented by fictitious switches. Suppose that instead they manifest an interior opposition ri0, which should then be included in succession after a while the switch in Figures 4.5(b)–(c). If the direct connected to the output node (y) is purely capacitive, earn ri feign the conclusive voltage of y or singly the duration needed for that voltage to quiet? Explain.