The questions below regard again the circuit of Figure E10.32. a. Intuitively, what voltage do you..


The questions under mind repeatedly the circumference of Figure E10.32.

a. Intuitively, what voltage do you foresee at node y when at lowest one input is '0'?

b. Say that N = 4 and that (W/L)n = 3(W/L)p (resumption from provision 9 that in this contingency n 9p). Consider also that VTn = 0.6 V, VTn = – 0.7 V, and VDD = 5 V. Calculate the output voltage (Vy) using twain expressions seen in the foregoing application.

c. Comment on the results overhead. Did they pair your foreseeations? In which regime (saturation or triode) do the nMOS and pMOS transistors in-effect produce?

d. Why cannot Vy always be 0 V?